Semiconductor devices, for example, microprocessors and chipsets, typically include a large number of terminals for supplying power, and for providing for input and output of electrical signals. Such terminals may be provided in an array on a surface of a device, which, when placed adjacent to and physically coupled to a corresponding array of terminals on a circuit substrate, such as a printed circuit board, may provide for conveyance of electrical signals between the device and other devices or power planes on the circuit substrate. The general trend in the industry is toward semiconductor devices operating at higher speeds and handling a greater number of signals, which has led to a corresponding trend toward designing an increasing number of power and I/O signal terminals into semiconductor devices. Simultaneously, semiconductor device manufacturers strive to contain the growth in the size of semiconductor devices, or even reduce them in size, to produce mobile electronic devices such as cellular phones, notebook computers, and digital media players. Therefore, in many instances, an increased number of terminals on a smaller or only nominally larger semiconductor device results in an increased density of terminals on a surface of the semiconductor device.
Some methods for meeting the design challenges of highly dense terminal arrays include shrinking the size of each terminal, and decreasing the pitch between adjacent terminals in an array. In some cases, ultra fine pitch terminal arrays may be formed. One of the challenges presented by such ultra fine pitch terminal arrays is that of forming reliable bonds between the terminals of a semiconductor device and a circuit substrate with the limited amounts of materials that may included as part of each terminal, without forming detrimental conductive bridging between adjacent terminals on either the semiconductor device or the circuit substrate. Electrolytic and chemical solder plating have been intensively studied in the electronics and semiconductor industries due to the low costs and relatively simple process involved. A few micrometers of plated solder on, for example, a metal bump or pad, can be produced using these plating techniques to provide an interconnection material for joining a terminal of a semiconductor device to that of a circuit substrate.
A short time after joining terminals, however, the relatively fast interdiffusion of elements of the metal bump and the plated solder, or of the pad and the plated solder, create a layer of ‘intermetallic compounds’ (IMC) at the bond line between the bump and the pad. IMC layers may be very brittle, and are recognized as a primary cause of joint failures when internal or external stress is applied to the bond. Examples of stresses commonly encountered include thermal stresses caused by differing coefficients of thermal expansion when the materials involved are exposed to thermal differentials during manufacturing or use, or physical stresses resulting from mechanical assembly processes and shipping and handling. Such stresses may be aggravated by poor coplanarity of terminals in an array of terminals.
Joint failures may include cracks propagating across a bond line and forming an ‘open’ circuit whereby a signal may be unable to travel across an air gap formed between the bump and the pad by the crack. In other cases, a crack across a bond line may result in the circuit being sometimes open and sometimes closed as the thermal, physical, or other conditions of a device change during use. In either case, the result may be at best an unreliably performing device, and at worst, a completely inoperative device. Attempts to resolve such reliability problems include such things as the use of an anisotropic conductive adhesive material. However, problems inherent in this approach include poor electrical performance due to water absorption and oxygen permeation, low impact strength due to high filler content, poor adhesion to copper, and poor long-term reliability performance.
Presently, the successful implementation of fine-pitch terminal arrays in semiconductor products, including the reliability of bonds formed with terminals, remains a substantial challenge.